Design of a Prototype ASIC for the MRPC Front-end Readout

The time of flight (TOF) detector is an important component of nuclear and particle physics experiments, and multi-gap resistive plate chamber (MRPC) is widely used in TOF measurement systems due to its high time precision. The mainstream technique for the readout of the MRPC detector involves amplification and discrimination, combined with a time-to-digital converter (TDC). To meet the requirements of high time precision, low power consumption, and high integration in MRPC readout electronics, a high-speed amplification and discrimination prototype chip has been designed. The chip integrates 8 channels, each of which includes a preamplifier, a discriminator, and an output driver circuit. The preamplifier adopts a common gate structure, facilitating impedance matching with low input impedance. The discriminator uses multiple cascaded amplifiers to provide enough gain, and achieves discrimination function by saturating amplification. After discrimination, the pulse signal is conveyed outside the chip via a low-voltage differential signaling (LVDS) driver, and its front edge and pulse width can characterize the time of arrival (TOA) and charge information of the MRPC signal. Based on 180 nm CMOS process, the circuit design, simulation and fabrication have been completed, and the performance test has been conducted in the laboratory environment. The test results indicate that the time precision is better than 10 ps (rms) with 100 fC~2 pC injected charge and the single channel power consumption is approximately 24 mW.