Abstract: High-precision time measurement technology is widely employed in high-energy physics experiments and nuclear physics experiments. To meet the demanding requirements of high precision and wide dynamic range for time measurement in the Time-of-Flight (TOF) detectors of the Radioactive Ion Beam Line in Lanzhou (RIBLL) at the Heavy Ion Research Facility in Lanzhou (HIRFL), a dual-channel Time-to-Digital Converter (TDC) has been implemented based on the Xilinx ZYNQ 7000 fully programmable 28nm System-on-Chip (SoC). This design adopts a combined method of "coarse counting" and "fine counting," utilizing cascaded Carry4 delay elements within the FPGA to construct a tapped delay line. During the design process, to address the "bubble" issue caused by uneven distribution of FPGA internal resources, an optimization algorithm based on Ones-Counter was implemented. To fulfill the requirements for high-speed data transmission, timestamp data from the TDC is transferred from the Programmable Logic (PL) section to the Processing System (PS) DDR memory via a Direct Memory Access (AXI DMA) controller. Ultimately, the PS section transmits the data to a host computer through TCP/IP protocol for calibration and alignment procedures. Testing results demonstrate that this TDC design achieves a maximum measurement range of 33.5 ms at a system clock frequency of 500 MHz, with a time resolution better than 15 ps. The differential nonlinearity (DNL) ranges from −0.01, 0.03 LSB, while the integral nonlinearity (INL) ranges from −0.01, 0.05 LSB. This design successfully realizes a high-precision time-to-digital converter with wide dynamic range and excellent linearity performance.