Abstract: Aiming at the technology of waveform digitization using high-speed analog-to-digital converter (ADC), a high-speed waveform digital sampling system is proposed to be designed using domestically produced low-speed ADC chips and Time interleaved A/D Conversion (TIADC) technology. The ADC splicing circuit design, JESD204B high-speed serial protocol data recombination method, and clock solution are introduced. However, there may be mismatch errors between different sampling channels, which can affect the performance of the system. Therefore this article introduces uses Particle Swarm Optimization (PSO) combined with Gradient Descent (GD) to estimate TIADC channel mismatch error. For mismatch errors, fractional delay FIR filter compensation reconstruction algorithm is used to achieve error calibration. The test results show that the system clock performance is stable and reliable. The system mismatch error is effectively compensated and calibrated. The performance of the TIADC system is significantly enhanced. The algorithm has the characteristics of fewer iterations and is easy to implement on FPGA. This waveform digitization technology can achieve real-time sampling and processing of nanosecond level signals, and provide technical support for the rapid development of physical experiments.