应用于像素探测器上的低功耗Pipeline SAR ADC设计

Design of Low Power Pipeline SAR ADC for Pixel Detectors

摘要: 基于180 nm CMOS工艺，设计了一款12 bit、40 MS/s的逐次逼近式流水线ADC芯片。芯片由两级SAR ADC，以及中间级余差放大器组成。为了降低功耗，SAR ADC使用了新型Sanyal开关切换策略，放大器使用了增益增强型运放。后仿真结果表明：在电源电压1.8 V，输入满摆幅−1~1 V，采样频率40 MS/s，输入信号频率12.93 MHz的情况下，ADC的有效位数可达10.73 bit，无杂散动态范围为75.7 dB，信号噪声与失真比为66.3 dB，总功耗约为9.2 mW。

Abstract: A 12-bit, 40 MS/s Pipeline SAR ADC chip was designed based on the 180 nm CMOS process. The chip consists of two stages of SAR ADCs and an inter-stage residue amplifier. To achieve low power consumption, the SAR ADC adopts a novel Sanyal switching scheme, and the amplifier employs a gain-boosted operational amplifier. Post-layout simulation results indicate that, under a 1.8 V power supply, with a full-scale input range of −1 V to 1 V, and sampling at 40 MS/s with a 12.93 MHz input signal, the ADC achieves an effective number of bits (ENOB) of 10.73 bits, a spurious-free dynamic range (SFDR) of 75.7 dB, and a signal-to-noise and distortion ratio (SNDR) of 66.3 dB. The total power consumption is approximately 9.2 mW.